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[PLARCH23] Fearless Hardware Design
"Fearless Hardware Design" - Rachit Nigam (Latch-Up 2023)
[PLARCH23] PEak: A Single Source of Truth for Hardware Design and Verification
[PLARCH23] Challenges with Hardware-Software Co-design for Sparse Machine Learning on (...) Dataflow
[PLARCH23] Semi-Automated Translation of a Formal ISA Specification to Hardware
The Essence of Bluespec - A Core Language for Rule Based Hardware Design
A Flexible Type System for Fearless Concurrency
Rachit Nigam presents "Predictable Accelerator Design with Time-Sensitive Affine Types
ASPLOS'23 - Session 8B - Stepwise Debugging for Hardware Accelerators
UMass CS Systems Lunch - Adrian Sampson (Cornell), Oct 2020
![[PLARCH23] Fearless Hardware Design](https://img.youtube.com/vi/VVCYnVsEuj0/hqdefault.jpg)
![[PLARCH23] PEak: A Single Source of Truth for Hardware Design and Verification](https://img.youtube.com/vi/f2phhjVvZMY/hqdefault.jpg)
![[PLARCH23] Challenges with Hardware-Software Co-design for Sparse Machine Learning on (...) Dataflow](https://img.youtube.com/vi/eiYtlmeSGCY/hqdefault.jpg)
![[PLARCH23] Semi-Automated Translation of a Formal ISA Specification to Hardware](https://img.youtube.com/vi/gZOyMVxPYlI/hqdefault.jpg)
